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The JBS-xx series IEEE 1149.1 (JTAG/Boundary Scan) programmers are provided on a custom basis. They are based loosely on the highly successful EMP line of device programmers. Along with the capability to handle in-circuit programming, additional functions can be included in the customers specification. These additional functions may include
partitioning, loading seed values for devices with BIST and/or loading internal values into device registers for performing test suites. With Boundary Scan as part of the design, non-design related structural faults can be easily detected. Connection to the Board or System Under Test is through the IEEE 1149.1 compliant 4 wire standard, the 5 wire
standard can also be supported. If higher than VCC programming voltages are required they may be included in the board design and turned on remotely or supplied directly from the JEMP programmer. Capabilities and specifications are developed on an individual basis usually during the Design For Test phase of a product design. Single and Multipath design
are possible.
The operating interface, JBS-Control, is DOS based or functions as a well-behaved DOS application under Windows*. The included buffer editor allows the data to be placed exactly where you want it and provides HEX and ASCII strings as well as support for SPLITS, SETS, and SWAPS.
Included is a flexible macro facility allowing frequently used procedures to be stored, then executed with a key stroke.
The heart of the hardware design is an SRAM based dynamic FPGA. Custom designed structures have a unique FPGA configuration file. This allows for multi-structure support with a single JEMP system. |
